The following relates generally to memory devices and more specifically to switching of magnetoresistive random access memory (MRAM) devices using fast pulse operation.
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.
Multiple types of memory devices exist, including magnetic hard disks, MRAM, spin-transfer torque (STT)-random access memory (RAM) (STT-RAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), read only memory (ROM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory (e.g., MRAM, STT-RAM, and PCM) may maintain stored logic states for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) may lose stored logic states over time unless they are periodically refreshed by an external power source. Improving memory devices may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.
Memory devices may access memory cells in a memory array via conductive paths that may be referred to as access lines. In some cases (e.g., in high density memory arrays), the access lines are constructed using narrow trace widths and placed close to one another to maximize the memory cell density of a memory array. Narrow trace widths may be associated with a higher inherent resistance of the access lines and the close line placement may be associated with a higher inherent capacitance between the access lines. Moreover, the access lines may extend from the periphery of the memory array to the center of a memory array to reach all of the memory cells in an effort to avoid partitioning the memory array into subarrays. As the length of the access lines increase, the inherent resistance of the access lines and the inherent capacitance between the access lines also increases.
Thus, the farther away a memory cell is located from a voltage or current source, the more the memory cell will potentially be affected by these parasitic elements during access operations. For example, a voltage generated by a voltage source located at a periphery of a memory array may be significantly more degraded by the time it reaches memory cells in the center of the memory array relative to memory cells located at the periphery of the memory array—e.g., a rise time of the applied voltage may be slowed, or a magnitude of the voltage may be attenuated, or both.